Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ahb_def_slave.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\BusMatrix.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_define.vh D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_static_macro_define.vh D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\can_top.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_adder.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ahb.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_alu_dec.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_core.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_ctl_add3.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_dec.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ahb_mux.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_bp.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_ctl.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_define.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_dw.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_dbg.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_mtx_sys.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_rom_tb.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_sys.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_tcm.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dbg_undefs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_decoder.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_defs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_dp.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_excpt.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fetch.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_fns.vh D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_matrix_check_fns.vh D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mem_ctl.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiplier.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_multiply_shift.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_mux4.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_ahb_os.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_defs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_main.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_lvl.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_pri_num.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_tree.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_nvic_undefs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_reg_bank.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_shifter.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cm1_undefs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_miim_wrapper.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_to_buffer.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_rx_wrapper.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_top.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_tx_wrapper.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_ethmac_wrapper.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_gpio.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_arbiter.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_async_fifo_clr.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_config.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_const.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_ctrl.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_fifo.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_gck.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_pad_lib.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_reg.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_regif_ctrl.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_spiif.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_l2l.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_spi_flash_sync_p2p.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_ahb_to_iop.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_defs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_dualtimers_frc.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_spi.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_timer.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_autocorrelation.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_balancefilter.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_collector.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_crngt_to_trng.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_inv_chain.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dx_trng_top.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_ff.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_interrupt_low.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_mux_clk.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_dxm_sync.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_ehr.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_entropy_gen.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_gtech_models.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_lfsr_new.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_line.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_noise_gen.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_pmf_table.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_prng_top_wrap.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_reg_file.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_engine.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_misc.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rosc.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_rst_logic.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sample_cntr.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_slave_bus_ifc.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_sync.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_tests_misc.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_trng_top.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_uart.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_defs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_apb_watchdog_frc.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\cmsdk_iop_gpio.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1Dbg.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegration.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\CortexM1DbgIntegrationWrapper.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapahbap.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApAhbSync.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDapSync.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApDefs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApMst.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSlv.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPAhbApSyn.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDecMux.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbDefs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpApbSync.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpEnSync.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpIMux.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPDpSync.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpDefs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPJtagDpProtocol.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpApbIf.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpDefs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpProtocol.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwDpSync.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dapswjdp.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjDpDefs.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DAPSwjWatcher.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_1_4code.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_define.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_name.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\ddr3_to_ahb_top.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\DDR3_TOP.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\dtcmdbg.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Gowin_EMPU_M1_top.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinAhbExt.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExt.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\GowinCM1AhbExtWrapper.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_ahb_psram.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_i2c.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_int_wrapper.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_apb_sd.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\gw_gpio.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\InputStage.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\itcmdbg.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS0.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS1.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\MatrixDecodeS2.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb1.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb2.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputArb3.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage1.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage2.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\OutputStage3.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_ahb_to_apb.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\p_sse050_interconnect_f0_apb_slave_mux.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_code.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\psram_top.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_addr_params.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_cc_params.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\rng_params.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\Rtc.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcApbif.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcControl.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcCounter.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcInterrupt.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcParams.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcRevAnd.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcSynctoPCLK.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\RtcUpdate.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_int_apb_decoder.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sse050_integration_peripherals.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\sync_p2p.v D:\Gowin\Gowin_V1.9.8.08\IDE\ipcore\GOWIN_EMPU_M1\data\debug\triple_speed_mac_name.v J:\Proekts_GoWin\Tang_Nano_9\Proba_IP\fpga_project\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v J:\Proekts_GoWin\Tang_Nano_9\Proba_IP\fpga_project\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v J:\Proekts_GoWin\Tang_Nano_9\Proba_IP\fpga_project\src\gowin_empu_m1\temp\gw_empu_m1\can_parameter.vh J:\Proekts_GoWin\Tang_Nano_9\Proba_IP\fpga_project\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v J:\Proekts_GoWin\Tang_Nano_9\Proba_IP\fpga_project\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v |
GowinSynthesis Constraints File | --- |
Version | GowinSynthesis V1.9.8.08 |
Part Number | GW1NR-LV9QN88PC6/I5 |
Device | GW1NR-9C |
Created Time | Thu Jun 15 12:03:11 2023 |
Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | Gowin_EMPU_M1_Top |
Synthesis Process | Running parser: CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 99.117MB Running netlist conversion: CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.287s, Peak memory usage = 99.117MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 99.117MB Optimizing Phase 1: CPU time = 0h 0m 0.577s, Elapsed time = 0h 0m 0.589s, Peak memory usage = 99.117MB Optimizing Phase 2: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 99.117MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.842s, Elapsed time = 0h 0m 0.846s, Peak memory usage = 99.117MB Inferring Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.113s, Peak memory usage = 99.117MB Inferring Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 99.117MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 99.117MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 99.117MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.4s, Peak memory usage = 99.117MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.78s, Elapsed time = 0h 0m 0.768s, Peak memory usage = 99.117MB Tech-Mapping Phase 3: CPU time = 0h 0m 57s, Elapsed time = 0h 0m 57s, Peak memory usage = 113.699MB Tech-Mapping Phase 4: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 113.699MB Generate output files: CPU time = 0h 0m 0.889s, Elapsed time = 0h 0m 0.933s, Peak memory usage = 113.699MB |
Total Time and Memory Usage | CPU time = 0h 1m 17s, Elapsed time = 0h 1m 17s, Peak memory usage = 113.699MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 38 |
I/O Buf | 38 |
    IBUF | 6 |
    OBUF | 15 |
    IOBUF | 17 |
Register | 2613 |
    DFF | 101 |
    DFFE | 32 |
    DFFSE | 1 |
    DFFR | 19 |
    DFFRE | 1 |
    DFFP | 30 |
    DFFPE | 86 |
    DFFC | 461 |
    DFFCE | 1881 |
    DFFNC | 1 |
LUT | 5682 |
    LUT2 | 452 |
    LUT3 | 1628 |
    LUT4 | 3602 |
ALU | 152 |
    ALU | 152 |
SSRAM | 20 |
    RAM16S4 | 4 |
    RAM16SDP4 | 16 |
INV | 27 |
    INV | 27 |
DSP | 1 |
    MULT36X36 | 1 |
BSRAM | 24 |
    DPB | 24 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 5981(5709 LUTs, 152 ALUs, 20 SSRAMs) / 8640 | 69% |
Register | 2613 / 6693 | 39% |
  --Register as Latch | 0 / 6693 | 0% |
  --Register as FF | 2613 / 6693 | 39% |
BSRAM | 24 / 26 | 92% |
Timing
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|
HCLK | Base | 20.000 | 50.0 | 0.000 | 10.000 | HCLK_ibuf/I | ||
JTAG_9 | Base | 20.000 | 50.0 | 0.000 | 10.000 | JTAG_9_ibuf/I |
Max Frequency Summary:
No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | HCLK | 50.0(MHz) | 53.3(MHz) | 14 | TOP |
2 | JTAG_9 | 50.0(MHz) | 67.0(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | -2.096 |
Data Arrival Time | 23.011 |
Data Required Time | 20.915 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.982 | 0.982 | tINS | RR | 324 | JTAG_9_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/CLK |
1.803 | 0.458 | tC2Q | RF | 15 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/Q |
2.283 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I1 |
3.382 | 1.099 | tINS | FF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
3.862 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
4.894 | 1.032 | tINS | FF | 100 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
5.374 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/I2 |
6.196 | 0.822 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/F |
6.676 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/I1 |
7.775 | 1.099 | tINS | FF | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/F |
8.255 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I1 |
9.354 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
9.834 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
10.933 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
11.413 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
12.445 | 1.032 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
12.925 | 0.480 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
13.970 | 1.045 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
13.970 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
14.027 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
14.027 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
14.084 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
14.564 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
15.386 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
15.866 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
16.965 | 1.099 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
17.445 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
18.544 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
19.024 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s7/I2 |
19.846 | 0.822 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s7/F |
20.326 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_1_s8/I1 |
21.425 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_1_s8/F |
21.905 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_1_s6/I3 |
22.531 | 0.626 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_1_s6/F |
23.011 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.982 | 0.982 | tINS | RR | 2358 | HCLK_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1/CLK |
21.315 | -0.030 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1 | ||
20.915 | -0.400 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 16 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 14.008, 64.654%; route: 7.200, 33.231%; tC2Q: 0.458, 2.115% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 2
Path Summary:Slack | -0.923 |
Data Arrival Time | 21.838 |
Data Required Time | 20.915 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.982 | 0.982 | tINS | RR | 324 | JTAG_9_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/CLK |
1.803 | 0.458 | tC2Q | RF | 15 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/Q |
2.283 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I1 |
3.382 | 1.099 | tINS | FF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
3.862 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
4.894 | 1.032 | tINS | FF | 100 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
5.374 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/I2 |
6.196 | 0.822 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/F |
6.676 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/I1 |
7.775 | 1.099 | tINS | FF | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/F |
8.255 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I1 |
9.354 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
9.834 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
10.933 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
11.413 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
12.445 | 1.032 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
12.925 | 0.480 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
13.970 | 1.045 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
13.970 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
14.027 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
14.027 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
14.084 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
14.564 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
15.386 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
15.866 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
16.965 | 1.099 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
17.445 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
18.477 | 1.032 | tINS | FF | 32 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
18.957 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_12_s1/I1 |
20.056 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_12_s1/F |
20.536 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_12_s0/I2 |
21.358 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_12_s0/F |
21.838 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.982 | 0.982 | tINS | RR | 2358 | HCLK_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0/CLK |
21.315 | -0.030 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0 | ||
20.915 | -0.400 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_12_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 13.315, 64.973%; route: 6.720, 32.791%; tC2Q: 0.458, 2.236% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 3
Path Summary:Slack | -0.923 |
Data Arrival Time | 21.838 |
Data Required Time | 20.915 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.982 | 0.982 | tINS | RR | 324 | JTAG_9_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/CLK |
1.803 | 0.458 | tC2Q | RF | 15 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/Q |
2.283 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I1 |
3.382 | 1.099 | tINS | FF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
3.862 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
4.894 | 1.032 | tINS | FF | 100 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
5.374 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/I2 |
6.196 | 0.822 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/F |
6.676 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/I1 |
7.775 | 1.099 | tINS | FF | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/F |
8.255 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I1 |
9.354 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
9.834 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
10.933 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
11.413 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
12.445 | 1.032 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
12.925 | 0.480 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
13.970 | 1.045 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
13.970 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
14.027 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
14.027 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
14.084 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
14.564 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
15.386 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
15.866 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
16.965 | 1.099 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
17.445 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
18.477 | 1.032 | tINS | FF | 32 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
18.957 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s1/I1 |
20.056 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s1/F |
20.536 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s0/I2 |
21.358 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s0/F |
21.838 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.982 | 0.982 | tINS | RR | 2358 | HCLK_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0/CLK |
21.315 | -0.030 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0 | ||
20.915 | -0.400 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 13.315, 64.973%; route: 6.720, 32.791%; tC2Q: 0.458, 2.236% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 4
Path Summary:Slack | -0.923 |
Data Arrival Time | 21.838 |
Data Required Time | 20.915 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.982 | 0.982 | tINS | RR | 324 | JTAG_9_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/CLK |
1.803 | 0.458 | tC2Q | RF | 15 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/Q |
2.283 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I1 |
3.382 | 1.099 | tINS | FF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
3.862 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
4.894 | 1.032 | tINS | FF | 100 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
5.374 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/I2 |
6.196 | 0.822 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/F |
6.676 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/I1 |
7.775 | 1.099 | tINS | FF | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/F |
8.255 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I1 |
9.354 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
9.834 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
10.933 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
11.413 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
12.445 | 1.032 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
12.925 | 0.480 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
13.970 | 1.045 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
13.970 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
14.027 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
14.027 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
14.084 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
14.564 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
15.386 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
15.866 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
16.965 | 1.099 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
17.445 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
18.477 | 1.032 | tINS | FF | 32 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
18.957 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s1/I1 |
20.056 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s1/F |
20.536 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s0/I2 |
21.358 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s0/F |
21.838 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.982 | 0.982 | tINS | RR | 2358 | HCLK_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0/CLK |
21.315 | -0.030 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0 | ||
20.915 | -0.400 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 13.315, 64.973%; route: 6.720, 32.791%; tC2Q: 0.458, 2.236% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 5
Path Summary:Slack | -0.923 |
Data Arrival Time | 21.838 |
Data Required Time | 20.915 |
From | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0 |
To | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0 |
Launch Clk | JTAG_9[R] |
Latch Clk | HCLK[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | JTAG_9 | |||
0.000 | 0.000 | tCL | RR | 1 | JTAG_9_ibuf/I |
0.982 | 0.982 | tINS | RR | 324 | JTAG_9_ibuf/O |
1.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/CLK |
1.803 | 0.458 | tC2Q | RF | 15 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_1_s0/Q |
2.283 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I1 |
3.382 | 1.099 | tINS | FF | 5 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
3.862 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
4.894 | 1.032 | tINS | FF | 100 | M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
5.374 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/I2 |
6.196 | 0.822 | tINS | FF | 3 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/BdSel_s1/F |
6.676 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/I1 |
7.775 | 1.099 | tINS | FF | 4 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s2/F |
8.255 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I1 |
9.354 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
9.834 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
10.933 | 1.099 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
11.413 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
12.445 | 1.032 | tINS | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
12.925 | 0.480 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
13.970 | 1.045 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
13.970 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
14.027 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
14.027 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
14.084 | 0.057 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
14.564 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
15.386 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
15.866 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
16.965 | 1.099 | tINS | FF | 8 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
17.445 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
18.477 | 1.032 | tINS | FF | 32 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
18.957 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_15_s1/I1 |
20.056 | 1.099 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_15_s1/F |
20.536 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_15_s0/I2 |
21.358 | 0.822 | tINS | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_15_s0/F |
21.838 | 0.480 | tNET | FF | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | HCLK | |||
20.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
20.982 | 0.982 | tINS | RR | 2358 | HCLK_ibuf/O |
21.345 | 0.363 | tNET | RR | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0/CLK |
21.315 | -0.030 | tUnc | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0 | ||
20.915 | -0.400 | tSu | 1 | M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_15_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 15 |
Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Arrival Data Path Delay: | cell: 13.315, 64.973%; route: 6.720, 32.791%; tC2Q: 0.458, 2.236% |
Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |