Timing Messages
Report Title | Timing Analysis Report |
Design File | J:\Proekts_GoWin\Tang_Nano_9\Proba_IP\fpga_project\impl\gwsynthesis\fpga_project.vg |
Physical Constraints File | J:\Proekts_GoWin\Tang_Nano_9\Proba_IP\fpga_project\src\FPGA_constr.cst |
Timing Constraint File | --- |
Version | V1.9.8.08 |
Part Number | GW1NR-LV9QN88PC6/I5 |
Device | GW1NR-9C |
Created Time | Thu Jun 15 13:25:03 2023 |
Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C C6/I5 |
Hold Delay Model | Fast 1.26V 0C C6/I5 |
Numbers of Paths Analyzed | 16780 |
Numbers of Endpoints Analyzed | 8534 |
Numbers of Falling Endpoints | 2 |
Numbers of Setup Violated Endpoints | 1170 |
Numbers of Hold Violated Endpoints | 2 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
sys_clk | Base | 37.037 | 27.000 | 0.000 | 18.519 | sys_clk_ibuf/I | ||
TCLK_JTAG_Soft | Base | 20.000 | 50.000 | 0.000 | 10.000 | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I | ||
clk_1kHz_4 | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_1kHz_s1/Q | ||
clk_2kHz_4 | Base | 20.000 | 50.000 | 0.000 | 10.000 | clk_2kHz_s1/Q | ||
Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | Generated | 18.519 | 54.000 | 0.000 | 9.259 | sys_clk_ibuf/I | sys_clk | Gowin_rPLL_1/rpll_inst/CLKOUT |
Gowin_rPLL_1/rpll_inst/CLKOUTP.default_gen_clk | Generated | 18.519 | 54.000 | 0.000 | 9.259 | sys_clk_ibuf/I | sys_clk | Gowin_rPLL_1/rpll_inst/CLKOUTP |
Gowin_rPLL_1/rpll_inst/CLKOUTD.default_gen_clk | Generated | 37.037 | 27.000 | 0.000 | 18.519 | sys_clk_ibuf/I | sys_clk | Gowin_rPLL_1/rpll_inst/CLKOUTD |
Gowin_rPLL_1/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 55.556 | 18.000 | 0.000 | 27.778 | sys_clk_ibuf/I | sys_clk | Gowin_rPLL_1/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | sys_clk | 27.000(MHz) | 187.835(MHz) | 3 | TOP |
2 | TCLK_JTAG_Soft | 50.000(MHz) | 39.350(MHz) | 5 | TOP |
3 | clk_2kHz_4 | 50.000(MHz) | 59.078(MHz) | 8 | TOP |
4 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | 54.000(MHz) | 41.955(MHz) | 12 | TOP |
No timing paths to get frequency of clk_1kHz_4!
No timing paths to get frequency of Gowin_rPLL_1/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of Gowin_rPLL_1/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of Gowin_rPLL_1/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
sys_clk | Setup | 0.000 | 0 |
sys_clk | Hold | 0.000 | 0 |
TCLK_JTAG_Soft | Setup | -2.707 | 1 |
TCLK_JTAG_Soft | Hold | 0.000 | 0 |
clk_1kHz_4 | Setup | 0.000 | 0 |
clk_1kHz_4 | Hold | 0.000 | 0 |
clk_2kHz_4 | Setup | 0.000 | 0 |
clk_2kHz_4 | Hold | 0.000 | 0 |
Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | Setup | -636.875 | 479 |
Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
Gowin_rPLL_1/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
Gowin_rPLL_1/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
Gowin_rPLL_1/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
Gowin_rPLL_1/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
Gowin_rPLL_1/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
Gowin_rPLL_1/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -26.482 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_16_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.354 |
2 | -26.375 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_3_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.604 |
3 | -26.375 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_6_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.604 |
4 | -26.205 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.077 |
5 | -26.175 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.047 |
6 | -26.155 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.027 |
7 | -26.101 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_0_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.330 |
8 | -26.101 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_5_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.330 |
9 | -26.099 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.971 |
10 | -26.096 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_2_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.325 |
11 | -26.050 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_1_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.278 |
12 | -26.050 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_4_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.278 |
13 | -26.050 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_7_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.278 |
14 | -26.050 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_8_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.278 |
15 | -26.031 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.903 |
16 | -26.006 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_9_s0/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.235 |
17 | -25.851 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.723 |
18 | -25.849 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1/CE | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 26.077 |
19 | -25.764 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.636 |
20 | -25.754 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.626 |
21 | -25.732 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.604 |
22 | -25.568 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.440 |
23 | -25.568 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.440 |
24 | -25.438 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_19_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.310 |
25 | -25.406 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.741 | 0.439 | 25.278 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -0.685 | n258_s2/I0 | clk_1kHz_s1/D | clk_1kHz_4:[R] | sys_clk:[R] | -0.000 | -1.029 | 0.374 |
2 | -0.333 | n302_s2/I0 | clk_2kHz_s1/D | clk_2kHz_4:[R] | sys_clk:[R] | -0.000 | -1.029 | 0.726 |
3 | 0.505 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0/D | TCLK_JTAG_Soft:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | -0.034 | 0.570 |
4 | 0.558 | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0/Q | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0/CE | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.573 |
5 | 0.559 | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HREADYOUT_s0/Q | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0/CE | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.574 |
6 | 0.561 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/haddr_en_reg_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/asel_ppb_reg_s0/CE | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.576 |
7 | 0.568 | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HREADYOUT_s0/Q | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0/CE | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.583 |
8 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync3/sync_reg_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
9 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_2_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync2/sync_reg_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
10 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_1_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync_reg_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
11 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync_reg_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync2_reg_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
12 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApDapSync/uAhbApDapSync0/sync_reg_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApDapSync/uAhbApDapSync1/sync2_reg_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
13 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_18_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_18_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
14 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_20_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_20_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
15 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_21_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_21_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
16 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_30_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_30_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
17 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_3_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_3_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
18 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_7_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_7_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
19 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_14_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_14_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
20 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_15_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_15_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
21 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_22_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_22_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
22 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_27_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_27_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
23 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_28_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_28_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
24 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/excpt_up_ipsr_de_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/excpt_up_ipsr_ex_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
25 | 0.570 | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/rst_fptr_align_de_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/halt_hold1_ex_s0/D | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 0.570 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -2.482 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/TDOi_s1/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[F] | 0.370 | -0.807 | 3.586 |
2 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
3 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync2_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
4 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
5 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync2_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
6 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
7 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync2_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
8 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
9 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CSYSPWRUPREQ_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
10 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CDBGPWRUPREQ_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
11 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busabort_cdc_check_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
12 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Optr_s2/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
13 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Busreqi_s1/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
14 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APdir_cdc_check_s1/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
15 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Iptr_s1/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
16 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Transapdp_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
17 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickyerr_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
18 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickycmp_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
19 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_0_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
20 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_1_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
21 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_0_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
22 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_1_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
23 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_2_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
24 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_3_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
25 | -2.480 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_4_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | TCLK_JTAG_Soft:[R] | 0.741 | -0.439 | 3.586 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
2 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync2_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
3 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
4 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync2_reg_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
5 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscmpi_cdc_check_s1/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
6 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_0_s3/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
7 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_1_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
8 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buserrori_cdc_check_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
9 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Busacki_cdc_check_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
10 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_0_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
11 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_1_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
12 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_2_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
13 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_3_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
14 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
15 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
16 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
17 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
18 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
19 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
20 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
21 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
22 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_0_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
23 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_1_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
24 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_2_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
25 | 2.095 | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_3_s0/CLEAR | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] | 0.000 | 0.000 | 2.110 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 7.621 | 8.871 | 1.250 | Low Pulse Width | clk_1kHz_4 | REG_LCD_STR1_POZ0_6_s0 |
2 | 7.621 | 8.871 | 1.250 | Low Pulse Width | clk_1kHz_4 | REG_LCD_STR1_POZ11_2_s0 |
3 | 7.621 | 8.871 | 1.250 | Low Pulse Width | clk_1kHz_4 | REG_LCD_STR1_POZ0_5_s1 |
4 | 7.708 | 8.958 | 1.250 | Low Pulse Width | clk_2kHz_4 | en_s0 |
5 | 7.708 | 8.958 | 1.250 | Low Pulse Width | clk_2kHz_4 | counter_s_9_s1 |
6 | 7.708 | 8.958 | 1.250 | Low Pulse Width | clk_2kHz_4 | counter_s_5_s1 |
7 | 7.708 | 8.958 | 1.250 | Low Pulse Width | clk_2kHz_4 | counter_s_3_s1 |
8 | 7.708 | 8.958 | 1.250 | Low Pulse Width | clk_2kHz_4 | counter_s_2_s1 |
9 | 7.708 | 8.958 | 1.250 | Low Pulse Width | clk_2kHz_4 | counter_s_4_s1 |
10 | 7.708 | 8.958 | 1.250 | Low Pulse Width | clk_2kHz_4 | counter_s_8_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -26.482 |
Data Arrival Time | 268.698 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_16_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.042 | 0.022 | tNET | FF | 1 | R6C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
264.141 | 1.099 | tINS | FF | 32 | R6C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
265.695 | 1.554 | tNET | FF | 1 | R3C9[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_16_s1/I1 |
266.794 | 1.099 | tINS | FF | 1 | R3C9[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_16_s1/F |
267.599 | 0.804 | tNET | FF | 1 | R4C10[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_16_s0/I2 |
268.698 | 1.099 | tINS | FF | 1 | R4C10[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_16_s0/F |
268.698 | 0.000 | tNET | FF | 1 | R4C10[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R4C10[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_16_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_16_s0 | |||
242.215 | -0.400 | tSu | 1 | R4C10[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_16_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 12.288, 46.626%; route: 13.608, 51.635%; tC2Q: 0.458, 1.739% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path2
Path Summary:
Slack | -26.375 |
Data Arrival Time | 268.947 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_3_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.947 | 1.492 | tNET | RR | 1 | R9C8[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R9C8[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_3_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_3_s0 | |||
242.572 | -0.043 | tSu | 1 | R9C8[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_3_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.377%; route: 14.872, 55.900%; tC2Q: 0.458, 1.723% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path3
Path Summary:
Slack | -26.375 |
Data Arrival Time | 268.947 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_6_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.947 | 1.492 | tNET | RR | 1 | R9C8[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_6_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R9C8[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_6_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_6_s0 | |||
242.572 | -0.043 | tSu | 1 | R9C8[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_6_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.377%; route: 14.872, 55.900%; tC2Q: 0.458, 1.723% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path4
Path Summary:
Slack | -26.205 |
Data Arrival Time | 268.420 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 2 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q |
244.748 | 1.946 | tNET | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/I3 |
245.570 | 0.822 | tINS | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/F |
246.705 | 1.135 | tNET | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/I3 |
247.737 | 1.032 | tINS | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/F |
248.706 | 0.969 | tNET | FF | 1 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/I2 |
249.528 | 0.822 | tINS | FF | 37 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/F |
251.556 | 2.028 | tNET | FF | 1 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/I1 |
252.588 | 1.032 | tINS | FF | 2 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/F |
254.696 | 2.108 | tNET | FF | 2 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/I1 |
255.741 | 1.045 | tINS | FF | 1 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/COUT |
255.741 | 0.000 | tNET | FF | 2 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/CIN |
255.798 | 0.057 | tINS | FF | 1 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/COUT |
255.798 | 0.000 | tNET | FF | 2 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/CIN |
255.855 | 0.057 | tINS | FF | 1 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/COUT |
255.855 | 0.000 | tNET | FF | 2 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/CIN |
255.912 | 0.057 | tINS | FF | 1 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/COUT |
255.912 | 0.000 | tNET | FF | 2 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/CIN |
255.969 | 0.057 | tINS | FF | 1 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/COUT |
255.969 | 0.000 | tNET | FF | 2 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/CIN |
256.026 | 0.057 | tINS | FF | 1 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/COUT |
256.026 | 0.000 | tNET | FF | 2 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/CIN |
256.083 | 0.057 | tINS | FF | 1 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/COUT |
256.083 | 0.000 | tNET | FF | 2 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/CIN |
256.140 | 0.057 | tINS | FF | 1 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/COUT |
256.708 | 0.568 | tNET | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/I0 |
257.807 | 1.099 | tINS | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/F |
259.096 | 1.289 | tNET | FF | 2 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/I0 |
260.054 | 0.958 | tINS | FF | 1 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/COUT |
260.054 | 0.000 | tNET | FF | 2 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/CIN |
260.111 | 0.057 | tINS | FF | 1 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/COUT |
260.111 | 0.000 | tNET | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/CIN |
260.168 | 0.057 | tINS | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/COUT |
262.025 | 1.856 | tNET | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/I2 |
262.847 | 0.822 | tINS | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/F |
263.668 | 0.821 | tNET | FF | 1 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/I2 |
264.294 | 0.626 | tINS | FF | 3 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/F |
264.310 | 0.016 | tNET | FF | 1 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/I2 |
265.342 | 1.032 | tINS | FF | 12 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/F |
267.321 | 1.979 | tNET | FF | 1 | R8C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s0/I3 |
268.420 | 1.099 | tINS | FF | 1 | R8C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s0/F |
268.420 | 0.000 | tNET | FF | 1 | R8C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0 | |||
242.215 | -0.400 | tSu | 1 | R8C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 10.902, 41.807%; route: 14.717, 56.435%; tC2Q: 0.458, 1.758% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path5
Path Summary:
Slack | -26.175 |
Data Arrival Time | 268.390 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 2 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q |
244.748 | 1.946 | tNET | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/I3 |
245.570 | 0.822 | tINS | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/F |
246.705 | 1.135 | tNET | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/I3 |
247.737 | 1.032 | tINS | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/F |
248.706 | 0.969 | tNET | FF | 1 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/I2 |
249.528 | 0.822 | tINS | FF | 37 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/F |
251.556 | 2.028 | tNET | FF | 1 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/I1 |
252.588 | 1.032 | tINS | FF | 2 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/F |
254.696 | 2.108 | tNET | FF | 2 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/I1 |
255.741 | 1.045 | tINS | FF | 1 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/COUT |
255.741 | 0.000 | tNET | FF | 2 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/CIN |
255.798 | 0.057 | tINS | FF | 1 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/COUT |
255.798 | 0.000 | tNET | FF | 2 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/CIN |
255.855 | 0.057 | tINS | FF | 1 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/COUT |
255.855 | 0.000 | tNET | FF | 2 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/CIN |
255.912 | 0.057 | tINS | FF | 1 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/COUT |
255.912 | 0.000 | tNET | FF | 2 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/CIN |
255.969 | 0.057 | tINS | FF | 1 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/COUT |
255.969 | 0.000 | tNET | FF | 2 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/CIN |
256.026 | 0.057 | tINS | FF | 1 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/COUT |
256.026 | 0.000 | tNET | FF | 2 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/CIN |
256.083 | 0.057 | tINS | FF | 1 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/COUT |
256.083 | 0.000 | tNET | FF | 2 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/CIN |
256.140 | 0.057 | tINS | FF | 1 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/COUT |
256.708 | 0.568 | tNET | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/I0 |
257.807 | 1.099 | tINS | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/F |
259.096 | 1.289 | tNET | FF | 2 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/I0 |
260.054 | 0.958 | tINS | FF | 1 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/COUT |
260.054 | 0.000 | tNET | FF | 2 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/CIN |
260.111 | 0.057 | tINS | FF | 1 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/COUT |
260.111 | 0.000 | tNET | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/CIN |
260.168 | 0.057 | tINS | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/COUT |
262.025 | 1.856 | tNET | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/I2 |
262.847 | 0.822 | tINS | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/F |
263.668 | 0.821 | tNET | FF | 1 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/I2 |
264.294 | 0.626 | tINS | FF | 3 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/F |
264.310 | 0.016 | tNET | FF | 1 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/I2 |
265.342 | 1.032 | tINS | FF | 12 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/F |
267.291 | 1.949 | tNET | FF | 1 | R8C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_9_s0/I3 |
268.390 | 1.099 | tINS | FF | 1 | R8C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_9_s0/F |
268.390 | 0.000 | tNET | FF | 1 | R8C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0 | |||
242.215 | -0.400 | tSu | 1 | R8C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 10.902, 41.855%; route: 14.687, 56.386%; tC2Q: 0.458, 1.760% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path6
Path Summary:
Slack | -26.155 |
Data Arrival Time | 268.370 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.042 | 0.022 | tNET | FF | 1 | R6C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
264.141 | 1.099 | tINS | FF | 32 | R6C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
265.695 | 1.554 | tNET | FF | 1 | R3C9[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s1/I1 |
266.727 | 1.032 | tINS | FF | 1 | R3C9[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s1/F |
267.548 | 0.821 | tNET | FF | 1 | R5C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s0/I2 |
268.370 | 0.822 | tINS | FF | 1 | R5C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_13_s0/F |
268.370 | 0.000 | tNET | FF | 1 | R5C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R5C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0 | |||
242.215 | -0.400 | tSu | 1 | R5C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_13_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.944, 45.891%; route: 13.625, 52.348%; tC2Q: 0.458, 1.761% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path7
Path Summary:
Slack | -26.101 |
Data Arrival Time | 268.673 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_0_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.673 | 1.218 | tNET | RR | 1 | R11C8[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R11C8[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_0_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_0_s0 | |||
242.572 | -0.043 | tSu | 1 | R11C8[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_0_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.819%; route: 14.597, 55.441%; tC2Q: 0.458, 1.741% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path8
Path Summary:
Slack | -26.101 |
Data Arrival Time | 268.673 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_5_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.673 | 1.218 | tNET | RR | 1 | R11C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_5_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R11C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_5_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_5_s0 | |||
242.572 | -0.043 | tSu | 1 | R11C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_5_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.819%; route: 14.597, 55.441%; tC2Q: 0.458, 1.741% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path9
Path Summary:
Slack | -26.099 |
Data Arrival Time | 268.314 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C10[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s7/I2 |
266.405 | 1.032 | tINS | FF | 2 | R8C10[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s7/F |
267.215 | 0.810 | tNET | FF | 1 | R6C9[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s6/I3 |
268.314 | 1.099 | tINS | FF | 1 | R6C9[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s6/F |
268.314 | 0.000 | tNET | FF | 1 | R6C9[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R6C9[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1 | |||
242.215 | -0.400 | tSu | 1 | R6C9[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_0_s1 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 12.154, 46.798%; route: 13.359, 51.437%; tC2Q: 0.458, 1.765% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path10
Path Summary:
Slack | -26.096 |
Data Arrival Time | 268.668 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_2_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.668 | 1.213 | tNET | RR | 1 | R11C10[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R11C10[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_2_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_2_s0 | |||
242.572 | -0.043 | tSu | 1 | R11C10[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_2_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.826%; route: 14.593, 55.433%; tC2Q: 0.458, 1.741% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path11
Path Summary:
Slack | -26.050 |
Data Arrival Time | 268.622 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_1_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.622 | 1.166 | tNET | RR | 1 | R9C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R9C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_1_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_1_s0 | |||
242.572 | -0.043 | tSu | 1 | R9C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_1_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.902%; route: 14.546, 55.354%; tC2Q: 0.458, 1.744% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path12
Path Summary:
Slack | -26.050 |
Data Arrival Time | 268.622 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_4_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.622 | 1.166 | tNET | RR | 1 | R9C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_4_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R9C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_4_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_4_s0 | |||
242.572 | -0.043 | tSu | 1 | R9C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_4_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.902%; route: 14.546, 55.354%; tC2Q: 0.458, 1.744% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path13
Path Summary:
Slack | -26.050 |
Data Arrival Time | 268.622 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_7_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.622 | 1.166 | tNET | RR | 1 | R9C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_7_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R9C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_7_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_7_s0 | |||
242.572 | -0.043 | tSu | 1 | R9C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_7_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.902%; route: 14.546, 55.354%; tC2Q: 0.458, 1.744% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path14
Path Summary:
Slack | -26.050 |
Data Arrival Time | 268.622 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_8_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.622 | 1.166 | tNET | RR | 1 | R9C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_8_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R9C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_8_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_8_s0 | |||
242.572 | -0.043 | tSu | 1 | R9C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_8_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.902%; route: 14.546, 55.354%; tC2Q: 0.458, 1.744% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path15
Path Summary:
Slack | -26.031 |
Data Arrival Time | 268.246 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 2 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q |
244.748 | 1.946 | tNET | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/I3 |
245.570 | 0.822 | tINS | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/F |
246.705 | 1.135 | tNET | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/I3 |
247.737 | 1.032 | tINS | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/F |
248.706 | 0.969 | tNET | FF | 1 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/I2 |
249.528 | 0.822 | tINS | FF | 37 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/F |
251.556 | 2.028 | tNET | FF | 1 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/I1 |
252.588 | 1.032 | tINS | FF | 2 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/F |
254.696 | 2.108 | tNET | FF | 2 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/I1 |
255.741 | 1.045 | tINS | FF | 1 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/COUT |
255.741 | 0.000 | tNET | FF | 2 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/CIN |
255.798 | 0.057 | tINS | FF | 1 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/COUT |
255.798 | 0.000 | tNET | FF | 2 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/CIN |
255.855 | 0.057 | tINS | FF | 1 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/COUT |
255.855 | 0.000 | tNET | FF | 2 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/CIN |
255.912 | 0.057 | tINS | FF | 1 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/COUT |
255.912 | 0.000 | tNET | FF | 2 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/CIN |
255.969 | 0.057 | tINS | FF | 1 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/COUT |
255.969 | 0.000 | tNET | FF | 2 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/CIN |
256.026 | 0.057 | tINS | FF | 1 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/COUT |
256.026 | 0.000 | tNET | FF | 2 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/CIN |
256.083 | 0.057 | tINS | FF | 1 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/COUT |
256.083 | 0.000 | tNET | FF | 2 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/CIN |
256.140 | 0.057 | tINS | FF | 1 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/COUT |
256.708 | 0.568 | tNET | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/I0 |
257.807 | 1.099 | tINS | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/F |
259.096 | 1.289 | tNET | FF | 2 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/I0 |
260.054 | 0.958 | tINS | FF | 1 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/COUT |
260.054 | 0.000 | tNET | FF | 2 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/CIN |
260.111 | 0.057 | tINS | FF | 1 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/COUT |
260.111 | 0.000 | tNET | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/CIN |
260.168 | 0.057 | tINS | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/COUT |
262.025 | 1.856 | tNET | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/I2 |
262.847 | 0.822 | tINS | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/F |
263.668 | 0.821 | tNET | FF | 1 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/I2 |
264.294 | 0.626 | tINS | FF | 3 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/F |
264.310 | 0.016 | tNET | FF | 1 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/I2 |
265.342 | 1.032 | tINS | FF | 12 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/F |
267.147 | 1.805 | tNET | FF | 1 | R8C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_7_s0/I3 |
268.246 | 1.099 | tINS | FF | 1 | R8C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_7_s0/F |
268.246 | 0.000 | tNET | FF | 1 | R8C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0 | |||
242.215 | -0.400 | tSu | 1 | R8C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 10.902, 42.087%; route: 14.543, 56.143%; tC2Q: 0.458, 1.769% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path16
Path Summary:
Slack | -26.006 |
Data Arrival Time | 268.578 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_9_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/I1 |
267.455 | 0.625 | tINS | FR | 10 | R6C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s0/F |
268.578 | 1.123 | tNET | RR | 1 | R3C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_9_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R3C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_9_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_9_s0 | |||
242.572 | -0.043 | tSu | 1 | R3C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaReg_cdc_check_9_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.274, 42.973%; route: 14.503, 55.280%; tC2Q: 0.458, 1.747% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path17
Path Summary:
Slack | -25.851 |
Data Arrival Time | 268.066 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C10[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s7/I2 |
266.405 | 1.032 | tINS | FF | 2 | R8C10[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_0_s7/F |
266.416 | 0.011 | tNET | FF | 1 | R8C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_1_s8/I1 |
267.238 | 0.822 | tINS | FF | 1 | R8C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_1_s8/F |
267.244 | 0.005 | tNET | FF | 1 | R8C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_1_s6/I3 |
268.066 | 0.822 | tINS | FF | 1 | R8C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextPackCtr_1_s6/F |
268.066 | 0.000 | tNET | FF | 1 | R8C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1 | |||
242.215 | -0.400 | tSu | 1 | R8C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 16 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 12.699, 49.369%; route: 12.565, 48.849%; tC2Q: 0.458, 1.782% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path18
Path Summary:
Slack | -25.849 |
Data Arrival Time | 268.420 |
Data Required Time | 242.572 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.532 | 0.511 | tNET | FF | 1 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/I1 |
264.564 | 1.032 | tINS | FF | 2 | R7C8[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s3/F |
265.373 | 0.810 | tNET | FF | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/I2 |
265.999 | 0.626 | tINS | FF | 2 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/TaWrEn_s1/F |
266.830 | 0.831 | tNET | FF | 1 | R6C9[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s3/I1 |
267.632 | 0.802 | tINS | FR | 2 | R6C9[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s3/F |
268.420 | 0.788 | tNET | RR | 1 | R8C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1 | |||
242.572 | -0.043 | tSu | 1 | R8C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/PackCtr_1_s1 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 11.451, 43.912%; route: 14.168, 54.331%; tC2Q: 0.458, 1.758% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path19
Path Summary:
Slack | -25.764 |
Data Arrival Time | 267.979 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 2 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q |
244.748 | 1.946 | tNET | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/I3 |
245.570 | 0.822 | tINS | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/F |
246.705 | 1.135 | tNET | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/I3 |
247.737 | 1.032 | tINS | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/F |
248.706 | 0.969 | tNET | FF | 1 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/I2 |
249.528 | 0.822 | tINS | FF | 37 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/F |
251.556 | 2.028 | tNET | FF | 1 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/I1 |
252.588 | 1.032 | tINS | FF | 2 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/F |
254.696 | 2.108 | tNET | FF | 2 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/I1 |
255.741 | 1.045 | tINS | FF | 1 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/COUT |
255.741 | 0.000 | tNET | FF | 2 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/CIN |
255.798 | 0.057 | tINS | FF | 1 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/COUT |
255.798 | 0.000 | tNET | FF | 2 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/CIN |
255.855 | 0.057 | tINS | FF | 1 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/COUT |
255.855 | 0.000 | tNET | FF | 2 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/CIN |
255.912 | 0.057 | tINS | FF | 1 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/COUT |
255.912 | 0.000 | tNET | FF | 2 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/CIN |
255.969 | 0.057 | tINS | FF | 1 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/COUT |
255.969 | 0.000 | tNET | FF | 2 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/CIN |
256.026 | 0.057 | tINS | FF | 1 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/COUT |
256.026 | 0.000 | tNET | FF | 2 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/CIN |
256.083 | 0.057 | tINS | FF | 1 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/COUT |
256.083 | 0.000 | tNET | FF | 2 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/CIN |
256.140 | 0.057 | tINS | FF | 1 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/COUT |
256.708 | 0.568 | tNET | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/I0 |
257.807 | 1.099 | tINS | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/F |
259.096 | 1.289 | tNET | FF | 2 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/I0 |
260.054 | 0.958 | tINS | FF | 1 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/COUT |
260.054 | 0.000 | tNET | FF | 2 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/CIN |
260.111 | 0.057 | tINS | FF | 1 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/COUT |
260.111 | 0.000 | tNET | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/CIN |
260.168 | 0.057 | tINS | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/COUT |
262.025 | 1.856 | tNET | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/I2 |
262.847 | 0.822 | tINS | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/F |
263.668 | 0.821 | tNET | FF | 1 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/I2 |
264.294 | 0.626 | tINS | FF | 3 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/F |
264.310 | 0.016 | tNET | FF | 1 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/I2 |
265.342 | 1.032 | tINS | FF | 12 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/F |
267.157 | 1.815 | tNET | FF | 1 | R8C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_5_s0/I3 |
267.979 | 0.822 | tINS | FF | 1 | R8C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_5_s0/F |
267.979 | 0.000 | tNET | FF | 1 | R8C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0 | |||
242.215 | -0.400 | tSu | 1 | R8C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 10.625, 41.446%; route: 14.553, 56.767%; tC2Q: 0.458, 1.788% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path20
Path Summary:
Slack | -25.754 |
Data Arrival Time | 267.969 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 2 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q |
244.748 | 1.946 | tNET | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/I3 |
245.570 | 0.822 | tINS | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/F |
246.705 | 1.135 | tNET | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/I3 |
247.737 | 1.032 | tINS | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/F |
248.706 | 0.969 | tNET | FF | 1 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/I2 |
249.528 | 0.822 | tINS | FF | 37 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/F |
251.556 | 2.028 | tNET | FF | 1 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/I1 |
252.588 | 1.032 | tINS | FF | 2 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/F |
254.696 | 2.108 | tNET | FF | 2 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/I1 |
255.741 | 1.045 | tINS | FF | 1 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/COUT |
255.741 | 0.000 | tNET | FF | 2 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/CIN |
255.798 | 0.057 | tINS | FF | 1 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/COUT |
255.798 | 0.000 | tNET | FF | 2 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/CIN |
255.855 | 0.057 | tINS | FF | 1 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/COUT |
255.855 | 0.000 | tNET | FF | 2 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/CIN |
255.912 | 0.057 | tINS | FF | 1 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/COUT |
255.912 | 0.000 | tNET | FF | 2 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/CIN |
255.969 | 0.057 | tINS | FF | 1 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/COUT |
255.969 | 0.000 | tNET | FF | 2 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/CIN |
256.026 | 0.057 | tINS | FF | 1 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/COUT |
256.026 | 0.000 | tNET | FF | 2 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/CIN |
256.083 | 0.057 | tINS | FF | 1 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/COUT |
256.083 | 0.000 | tNET | FF | 2 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/CIN |
256.140 | 0.057 | tINS | FF | 1 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/COUT |
256.708 | 0.568 | tNET | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/I0 |
257.807 | 1.099 | tINS | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/F |
259.096 | 1.289 | tNET | FF | 2 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/I0 |
260.054 | 0.958 | tINS | FF | 1 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/COUT |
260.054 | 0.000 | tNET | FF | 2 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/CIN |
260.111 | 0.057 | tINS | FF | 1 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/COUT |
260.111 | 0.000 | tNET | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/CIN |
260.168 | 0.057 | tINS | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/COUT |
262.025 | 1.856 | tNET | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/I2 |
262.847 | 0.822 | tINS | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/F |
263.668 | 0.821 | tNET | FF | 1 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/I2 |
264.294 | 0.626 | tINS | FF | 3 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/F |
264.310 | 0.016 | tNET | FF | 1 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/I2 |
265.342 | 1.032 | tINS | FF | 12 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/F |
267.147 | 1.805 | tNET | FF | 1 | R8C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_8_s0/I3 |
267.969 | 0.822 | tINS | FF | 1 | R8C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_8_s0/F |
267.969 | 0.000 | tNET | FF | 1 | R8C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0 | |||
242.215 | -0.400 | tSu | 1 | R8C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 10.625, 41.461%; route: 14.543, 56.750%; tC2Q: 0.458, 1.789% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path21
Path Summary:
Slack | -25.732 |
Data Arrival Time | 267.947 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 2 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q |
244.748 | 1.946 | tNET | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/I3 |
245.570 | 0.822 | tINS | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/F |
246.705 | 1.135 | tNET | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/I3 |
247.737 | 1.032 | tINS | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/F |
248.706 | 0.969 | tNET | FF | 1 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/I2 |
249.528 | 0.822 | tINS | FF | 37 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/F |
251.556 | 2.028 | tNET | FF | 1 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/I1 |
252.588 | 1.032 | tINS | FF | 2 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/F |
254.696 | 2.108 | tNET | FF | 2 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/I1 |
255.741 | 1.045 | tINS | FF | 1 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/COUT |
255.741 | 0.000 | tNET | FF | 2 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/CIN |
255.798 | 0.057 | tINS | FF | 1 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/COUT |
255.798 | 0.000 | tNET | FF | 2 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/CIN |
255.855 | 0.057 | tINS | FF | 1 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/COUT |
255.855 | 0.000 | tNET | FF | 2 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/CIN |
255.912 | 0.057 | tINS | FF | 1 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/COUT |
255.912 | 0.000 | tNET | FF | 2 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/CIN |
255.969 | 0.057 | tINS | FF | 1 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/COUT |
255.969 | 0.000 | tNET | FF | 2 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/CIN |
256.026 | 0.057 | tINS | FF | 1 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/COUT |
256.026 | 0.000 | tNET | FF | 2 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/CIN |
256.083 | 0.057 | tINS | FF | 1 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/COUT |
256.083 | 0.000 | tNET | FF | 2 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/CIN |
256.140 | 0.057 | tINS | FF | 1 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/COUT |
256.708 | 0.568 | tNET | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/I0 |
257.807 | 1.099 | tINS | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/F |
259.096 | 1.289 | tNET | FF | 2 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/I0 |
260.054 | 0.958 | tINS | FF | 1 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/COUT |
260.054 | 0.000 | tNET | FF | 2 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/CIN |
260.111 | 0.057 | tINS | FF | 1 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/COUT |
260.111 | 0.000 | tNET | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/CIN |
260.168 | 0.057 | tINS | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/COUT |
262.025 | 1.856 | tNET | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/I2 |
262.847 | 0.822 | tINS | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/F |
263.668 | 0.821 | tNET | FF | 1 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/I2 |
264.294 | 0.626 | tINS | FF | 3 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/F |
264.310 | 0.016 | tNET | FF | 1 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/I2 |
265.342 | 1.032 | tINS | FF | 12 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/F |
267.321 | 1.979 | tNET | FF | 1 | R8C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_10_s0/I3 |
267.947 | 0.626 | tINS | FF | 1 | R8C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_10_s0/F |
267.947 | 0.000 | tNET | FF | 1 | R8C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0 | |||
242.215 | -0.400 | tSu | 1 | R8C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 10.429, 40.732%; route: 14.717, 57.478%; tC2Q: 0.458, 1.790% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path22
Path Summary:
Slack | -25.568 |
Data Arrival Time | 267.783 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 2 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q |
244.748 | 1.946 | tNET | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/I3 |
245.570 | 0.822 | tINS | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/F |
246.705 | 1.135 | tNET | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/I3 |
247.737 | 1.032 | tINS | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/F |
248.706 | 0.969 | tNET | FF | 1 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/I2 |
249.528 | 0.822 | tINS | FF | 37 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/F |
251.556 | 2.028 | tNET | FF | 1 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/I1 |
252.588 | 1.032 | tINS | FF | 2 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/F |
254.696 | 2.108 | tNET | FF | 2 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/I1 |
255.741 | 1.045 | tINS | FF | 1 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/COUT |
255.741 | 0.000 | tNET | FF | 2 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/CIN |
255.798 | 0.057 | tINS | FF | 1 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/COUT |
255.798 | 0.000 | tNET | FF | 2 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/CIN |
255.855 | 0.057 | tINS | FF | 1 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/COUT |
255.855 | 0.000 | tNET | FF | 2 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/CIN |
255.912 | 0.057 | tINS | FF | 1 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/COUT |
255.912 | 0.000 | tNET | FF | 2 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/CIN |
255.969 | 0.057 | tINS | FF | 1 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/COUT |
255.969 | 0.000 | tNET | FF | 2 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/CIN |
256.026 | 0.057 | tINS | FF | 1 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/COUT |
256.026 | 0.000 | tNET | FF | 2 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/CIN |
256.083 | 0.057 | tINS | FF | 1 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/COUT |
256.083 | 0.000 | tNET | FF | 2 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/CIN |
256.140 | 0.057 | tINS | FF | 1 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/COUT |
256.708 | 0.568 | tNET | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/I0 |
257.807 | 1.099 | tINS | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/F |
259.096 | 1.289 | tNET | FF | 2 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/I0 |
260.054 | 0.958 | tINS | FF | 1 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/COUT |
260.054 | 0.000 | tNET | FF | 2 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/CIN |
260.111 | 0.057 | tINS | FF | 1 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/COUT |
260.111 | 0.000 | tNET | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/CIN |
260.168 | 0.057 | tINS | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/COUT |
262.025 | 1.856 | tNET | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/I2 |
262.847 | 0.822 | tINS | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/F |
263.668 | 0.821 | tNET | FF | 1 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/I2 |
264.294 | 0.626 | tINS | FF | 3 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/F |
264.310 | 0.016 | tNET | FF | 1 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/I2 |
265.342 | 1.032 | tINS | FF | 12 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/F |
267.157 | 1.815 | tNET | FF | 1 | R8C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_4_s0/I3 |
267.783 | 0.626 | tINS | FF | 1 | R8C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_4_s0/F |
267.783 | 0.000 | tNET | FF | 1 | R8C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0 | |||
242.215 | -0.400 | tSu | 1 | R8C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 10.429, 40.994%; route: 14.553, 57.204%; tC2Q: 0.458, 1.802% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path23
Path Summary:
Slack | -25.568 |
Data Arrival Time | 267.783 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 2 | R3C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APsel_4_s0/Q |
244.748 | 1.946 | tNET | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/I3 |
245.570 | 0.822 | tINS | FF | 1 | R5C6[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s11/F |
246.705 | 1.135 | tNET | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/I3 |
247.737 | 1.032 | tINS | FF | 1 | R4C6[3][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s6/F |
248.706 | 0.969 | tNET | FF | 1 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/I2 |
249.528 | 0.822 | tINS | FF | 37 | R13C6[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbCtlEn_s3/F |
251.556 | 2.028 | tNET | FF | 1 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/I1 |
252.588 | 1.032 | tINS | FF | 2 | R8C7[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_dapdecmux/DAPRDATA_Z_8_s0/F |
254.696 | 2.108 | tNET | FF | 2 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/I1 |
255.741 | 1.045 | tINS | FF | 1 | R13C4[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n121_s0/COUT |
255.741 | 0.000 | tNET | FF | 2 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/CIN |
255.798 | 0.057 | tINS | FF | 1 | R13C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n122_s0/COUT |
255.798 | 0.000 | tNET | FF | 2 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/CIN |
255.855 | 0.057 | tINS | FF | 1 | R13C4[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n123_s0/COUT |
255.855 | 0.000 | tNET | FF | 2 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/CIN |
255.912 | 0.057 | tINS | FF | 1 | R13C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n124_s0/COUT |
255.912 | 0.000 | tNET | FF | 2 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/CIN |
255.969 | 0.057 | tINS | FF | 1 | R13C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n125_s0/COUT |
255.969 | 0.000 | tNET | FF | 2 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/CIN |
256.026 | 0.057 | tINS | FF | 1 | R13C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n126_s0/COUT |
256.026 | 0.000 | tNET | FF | 2 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/CIN |
256.083 | 0.057 | tINS | FF | 1 | R13C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n127_s0/COUT |
256.083 | 0.000 | tNET | FF | 2 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/CIN |
256.140 | 0.057 | tINS | FF | 1 | R13C5[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n128_s0/COUT |
256.708 | 0.568 | tNET | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/I0 |
257.807 | 1.099 | tINS | FF | 1 | R13C5[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Cmplane_1_s2/F |
259.096 | 1.289 | tNET | FF | 2 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/I0 |
260.054 | 0.958 | tINS | FF | 1 | R14C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n152_s0/COUT |
260.054 | 0.000 | tNET | FF | 2 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/CIN |
260.111 | 0.057 | tINS | FF | 1 | R14C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n153_s0/COUT |
260.111 | 0.000 | tNET | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/CIN |
260.168 | 0.057 | tINS | FF | 2 | R14C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/n154_s0/COUT |
262.025 | 1.856 | tNET | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/I2 |
262.847 | 0.822 | tINS | FF | 1 | R11C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s3/F |
263.668 | 0.821 | tNET | FF | 1 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/I2 |
264.294 | 0.626 | tINS | FF | 3 | R9C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntEn_s2/F |
264.310 | 0.016 | tNET | FF | 1 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/I2 |
265.342 | 1.032 | tINS | FF | 12 | R9C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_11_s3/F |
267.157 | 1.815 | tNET | FF | 1 | R8C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_6_s0/I3 |
267.783 | 0.626 | tINS | FF | 1 | R8C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/BuscntD_6_s0/F |
267.783 | 0.000 | tNET | FF | 1 | R8C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R8C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0 | |||
242.215 | -0.400 | tSu | 1 | R8C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 10.429, 40.994%; route: 14.553, 57.204%; tC2Q: 0.458, 1.802% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path24
Path Summary:
Slack | -25.438 |
Data Arrival Time | 267.653 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_19_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.042 | 0.022 | tNET | FF | 1 | R6C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
264.141 | 1.099 | tINS | FF | 32 | R6C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
265.516 | 1.375 | tNET | FF | 1 | R4C10[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_19_s1/I1 |
266.615 | 1.099 | tINS | FF | 1 | R4C10[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_19_s1/F |
266.621 | 0.005 | tNET | FF | 1 | R4C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_19_s0/I2 |
267.653 | 1.032 | tINS | FF | 1 | R4C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_19_s0/F |
267.653 | 0.000 | tNET | FF | 1 | R4C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_19_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R4C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_19_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_19_s0 | |||
242.215 | -0.400 | tSu | 1 | R4C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_19_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 12.221, 48.286%; route: 12.630, 49.903%; tC2Q: 0.458, 1.811% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Path25
Path Summary:
Slack | -25.406 |
Data Arrival Time | 267.622 |
Data Required Time | 242.215 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.000 | 240.000 | active clock edge time | ||||
240.000 | 0.000 | TCLK_JTAG_Soft | ||||
240.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
240.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
242.343 | 1.361 | tNET | RR | 1 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/CLK |
242.801 | 0.458 | tC2Q | RF | 14 | R15C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/State_cdc_check_3_s0/Q |
243.630 | 0.828 | tNET | FF | 1 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/I3 |
244.451 | 0.822 | tINS | FF | 5 | R15C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s1/F |
245.271 | 0.820 | tNET | FF | 1 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/I0 |
246.093 | 0.822 | tINS | FF | 100 | R16C3[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwjWatcher/iDBGDI_s0/F |
248.776 | 2.682 | tNET | FF | 1 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/I3 |
249.808 | 1.032 | tINS | FF | 3 | R7C5[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/CswSwWrEn_s3/F |
250.623 | 0.815 | tNET | FF | 1 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/I0 |
251.655 | 1.032 | tINS | FF | 4 | R6C7[3][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapSlvErr_s3/F |
253.610 | 1.955 | tNET | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/I2 |
254.432 | 0.822 | tINS | FF | 1 | R8C9[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s24/F |
255.236 | 0.804 | tNET | FF | 1 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/I1 |
256.058 | 0.822 | tINS | FF | 2 | R8C7[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s22/F |
256.868 | 0.810 | tNET | FF | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/I0 |
257.494 | 0.626 | tINS | FF | 2 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextState_1_s29/F |
258.635 | 1.141 | tNET | FF | 2 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/I1 |
259.680 | 1.045 | tINS | FF | 1 | R7C10[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n364_s0/COUT |
259.680 | 0.000 | tNET | FF | 2 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/CIN |
259.737 | 0.057 | tINS | FF | 1 | R7C10[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n365_s0/COUT |
259.737 | 0.000 | tNET | FF | 2 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/CIN |
259.794 | 0.057 | tINS | FF | 1 | R7C10[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n366_s0/COUT |
261.161 | 1.367 | tNET | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/I2 |
262.193 | 1.032 | tINS | FF | 1 | R6C8[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s2/F |
262.199 | 0.005 | tNET | FF | 1 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/I1 |
263.021 | 0.822 | tINS | FF | 8 | R6C8[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/n527_s1/F |
263.042 | 0.022 | tNET | FF | 1 | R6C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/I0 |
264.141 | 1.099 | tINS | FF | 32 | R6C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_1_s4/F |
265.695 | 1.554 | tNET | FF | 1 | R3C9[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s1/I1 |
266.794 | 1.099 | tINS | FF | 1 | R3C9[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s1/F |
266.800 | 0.005 | tNET | FF | 1 | R3C9[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s0/I2 |
267.622 | 0.822 | tINS | FF | 1 | R3C9[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/NextDapRdData_14_s0/F |
267.622 | 0.000 | tNET | FF | 1 | R3C9[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
240.741 | 240.741 | active clock edge time | ||||
240.741 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
242.401 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
242.645 | 0.244 | tNET | RR | 1 | R3C9[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0/CLK |
242.615 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0 | |||
242.215 | -0.400 | tSu | 1 | R3C9[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DAPRDATA_14_s0 |
Path Statistics:
Clock Skew | -0.439 |
Setup Relationship | 0.741 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Arrival Data Path Delay | cell: 12.011, 47.515%; route: 12.809, 50.672%; tC2Q: 0.458, 1.813% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -0.685 |
Data Arrival Time | 1000.374 |
Data Required Time | 1001.059 |
From | n258_s2 |
To | clk_1kHz_s1 |
Launch Clk | clk_1kHz_4:[R] |
Latch Clk | sys_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1000.000 | 1000.000 | active clock edge time | ||||
1000.000 | 0.000 | clk_1kHz_4 | ||||
1000.000 | 0.000 | tCL | RR | 5 | R20C43[0][A] | clk_1kHz_s1/Q |
1000.002 | 0.002 | tNET | RR | 1 | R20C43[0][A] | n258_s2/I0 |
1000.374 | 0.372 | tINS | RF | 1 | R20C43[0][A] | n258_s2/F |
1000.374 | 0.000 | tNET | FF | 1 | R20C43[0][A] | clk_1kHz_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1000.000 | 1000.000 | active clock edge time | ||||
1000.000 | 0.000 | sys_clk | ||||
1000.000 | 0.000 | tCL | RR | 1 | IOR17[A] | sys_clk_ibuf/I |
1000.844 | 0.844 | tINS | RR | 35 | IOR17[A] | sys_clk_ibuf/O |
1001.029 | 0.185 | tNET | RR | 1 | R20C43[0][A] | clk_1kHz_s1/CLK |
1001.059 | 0.030 | tUnc | clk_1kHz_s1 | |||
1001.059 | 0.000 | tHld | 1 | R20C43[0][A] | clk_1kHz_s1 |
Path Statistics:
Clock Skew | 1.029 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.372, 99.369%; route: 0.000, 0.000%; tC2Q: 0.002, 0.631% |
Required Clock Path Delay | cell: 0.844, 82.061%; route: 0.185, 17.939% |
Path2
Path Summary:
Slack | -0.333 |
Data Arrival Time | 1000.726 |
Data Required Time | 1001.059 |
From | n302_s2 |
To | clk_2kHz_s1 |
Launch Clk | clk_2kHz_4:[R] |
Latch Clk | sys_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1000.000 | 1000.000 | active clock edge time | ||||
1000.000 | 0.000 | clk_2kHz_4 | ||||
1000.000 | 0.000 | tCL | RR | 30 | R25C46[0][B] | clk_2kHz_s1/Q |
1000.002 | 0.002 | tNET | RR | 1 | R25C46[0][B] | n302_s2/I0 |
1000.726 | 0.724 | tINS | RR | 1 | R25C46[0][B] | n302_s2/F |
1000.726 | 0.000 | tNET | RR | 1 | R25C46[0][B] | clk_2kHz_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1000.000 | 1000.000 | active clock edge time | ||||
1000.000 | 0.000 | sys_clk | ||||
1000.000 | 0.000 | tCL | RR | 1 | IOR17[A] | sys_clk_ibuf/I |
1000.844 | 0.844 | tINS | RR | 35 | IOR17[A] | sys_clk_ibuf/O |
1001.029 | 0.185 | tNET | RR | 1 | R25C46[0][B] | clk_2kHz_s1/CLK |
1001.059 | 0.030 | tUnc | clk_2kHz_s1 | |||
1001.059 | 0.000 | tHld | 1 | R25C46[0][B] | clk_2kHz_s1 |
Path Statistics:
Clock Skew | 1.029 |
Hold Relationship | -0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.724, 99.675%; route: 0.000, 0.000%; tC2Q: 0.002, 0.325% |
Required Clock Path Delay | cell: 0.844, 82.061%; route: 0.185, 17.939% |
Path3
Path Summary:
Slack | 0.505 |
Data Arrival Time | 2.380 |
Data Required Time | 1.875 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0 |
Launch Clk | TCLK_JTAG_Soft:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | TCLK_JTAG_Soft | ||||
0.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
0.844 | 0.844 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
1.811 | 0.966 | tNET | RR | 1 | R5C2[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0/CLK |
2.144 | 0.333 | tC2Q | RR | 1 | R5C2[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0/Q |
2.380 | 0.236 | tNET | RR | 1 | R5C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R5C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0/CLK |
1.875 | 0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0 | |||
1.875 | 0.000 | tHld | 1 | R5C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0 |
Path Statistics:
Clock Skew | 0.034 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.844, 46.631%; route: 0.966, 53.369% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path4
Path Summary:
Slack | 0.558 |
Data Arrival Time | 2.418 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0 |
To | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R3C45[1][A] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 5 | R3C45[1][A] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0/Q |
2.418 | 0.240 | tNET | RR | 1 | R3C45[0][A] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R3C45[0][A] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0/CLK |
1.860 | 0.015 | tHld | 1 | R3C45[0][A] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.240, 41.854%; tC2Q: 0.333, 58.146% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path5
Path Summary:
Slack | 0.559 |
Data Arrival Time | 2.420 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HREADYOUT_s0 |
To | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R3C46[0][B] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HREADYOUT_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 6 | R3C46[0][B] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HREADYOUT_s0/Q |
2.420 | 0.241 | tNET | RR | 1 | R3C46[1][A] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R3C46[1][A] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0/CLK |
1.860 | 0.015 | tHld | 1 | R3C46[1][A] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.241, 41.973%; tC2Q: 0.333, 58.027% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path6
Path Summary:
Slack | 0.561 |
Data Arrival Time | 2.421 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/haddr_en_reg_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/asel_ppb_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C32[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/haddr_en_reg_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 2 | R7C32[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/haddr_en_reg_s0/Q |
2.421 | 0.243 | tNET | RR | 1 | R7C32[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/asel_ppb_reg_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C32[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/asel_ppb_reg_s0/CLK |
1.860 | 0.015 | tHld | 1 | R7C32[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/asel_ppb_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.243, 42.123%; tC2Q: 0.333, 57.877% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path7
Path Summary:
Slack | 0.568 |
Data Arrival Time | 2.428 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HREADYOUT_s0 |
To | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R2C46[0][B] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HREADYOUT_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 4 | R2C46[0][B] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HREADYOUT_s0/Q |
2.428 | 0.250 | tNET | RR | 1 | R2C46[2][B] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R2C46[2][B] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0/CLK |
1.860 | 0.015 | tHld | 1 | R2C46[2][B] | Gowin_EMPU_M1_Top_1/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.250, 42.857%; tC2Q: 0.333, 57.143% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path8
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync3/sync_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_3_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R8C9[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_3_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync3/sync_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync3/sync_reg_s0/CLK |
1.845 | 0.000 | tHld | 1 | R8C9[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync3/sync_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path9
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_2_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync2/sync_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C10[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_2_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R8C10[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_2_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R8C10[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync2/sync_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C10[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync2/sync_reg_s0/CLK |
1.845 | 0.000 | tHld | 1 | R8C10[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync2/sync_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path10
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_1_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C8[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_1_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R7C8[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/DapState_cdc_check_1_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R7C8[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C8[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync_reg_s0/CLK |
1.845 | 0.000 | tHld | 1 | R7C8[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path11
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync_reg_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync2_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C8[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync_reg_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R7C8[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync_reg_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync2_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync2_reg_s0/CLK |
1.845 | 0.000 | tHld | 1 | R7C8[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApAhbSync/uAhbApAhbSync1/sync2_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path12
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApDapSync/uAhbApDapSync0/sync_reg_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApDapSync/uAhbApDapSync1/sync2_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApDapSync/uAhbApDapSync0/sync_reg_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R7C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApDapSync/uAhbApDapSync0/sync_reg_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R7C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApDapSync/uAhbApDapSync1/sync2_reg_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApDapSync/uAhbApDapSync1/sync2_reg_s0/CLK |
1.845 | 0.000 | tHld | 1 | R7C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApDapSync/uAhbApDapSync1/sync2_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path13
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_18_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_18_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R5C7[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_18_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R5C7[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_18_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R5C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R5C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_18_s0/CLK |
1.845 | 0.000 | tHld | 1 | R5C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path14
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_20_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_20_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R6C7[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_20_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R6C7[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_20_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R6C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_20_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R6C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_20_s0/CLK |
1.845 | 0.000 | tHld | 1 | R6C7[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_20_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path15
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_21_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_21_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R6C7[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_21_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R6C7[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_21_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R6C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_21_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R6C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_21_s0/CLK |
1.845 | 0.000 | tHld | 1 | R6C7[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_21_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path16
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_30_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_30_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C11[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_30_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R7C11[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApSlv/AhbWrData_cdc_check_30_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R7C11[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_30_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R7C11[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_30_s0/CLK |
1.845 | 0.000 | tHld | 1 | R7C11[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_dap_ahb_ap/uDAPAhbApMst/HWDATAM_30_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path17
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_3_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_3_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C35[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_3_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R8C35[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_3_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R8C35[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C35[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_3_s0/CLK |
1.845 | 0.000 | tHld | 1 | R8C35[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path18
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_7_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_7_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C36[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_7_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R9C36[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_7_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R9C36[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C36[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_7_s0/CLK |
1.845 | 0.000 | tHld | 1 | R9C36[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path19
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_14_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_14_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C35[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_14_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R8C35[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_14_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R8C35[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C35[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_14_s0/CLK |
1.845 | 0.000 | tHld | 1 | R8C35[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path20
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_15_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_15_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C37[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_15_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R9C37[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_15_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R9C37[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C37[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_15_s0/CLK |
1.845 | 0.000 | tHld | 1 | R9C37[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path21
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_22_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_22_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R6C33[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_22_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R6C33[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_22_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R6C33[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_22_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R6C33[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_22_s0/CLK |
1.845 | 0.000 | tHld | 1 | R6C33[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_22_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path22
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_27_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_27_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C35[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_27_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R9C35[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_27_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R9C35[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_27_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C35[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_27_s0/CLK |
1.845 | 0.000 | tHld | 1 | R9C35[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_27_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path23
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_28_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_28_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C35[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_28_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R9C35[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/wdata_28_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R9C35[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_28_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C35[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_28_s0/CLK |
1.845 | 0.000 | tHld | 1 | R9C35[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_ahb/HWDATA_28_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path24
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/excpt_up_ipsr_de_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/excpt_up_ipsr_ex_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R14C26[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/excpt_up_ipsr_de_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R14C26[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/excpt_up_ipsr_de_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R14C26[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/excpt_up_ipsr_ex_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R14C26[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/excpt_up_ipsr_ex_s0/CLK |
1.845 | 0.000 | tHld | 1 | R14C26[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/excpt_up_ipsr_ex_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path25
Path Summary:
Slack | 0.570 |
Data Arrival Time | 2.415 |
Data Required Time | 1.845 |
From | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/rst_fptr_align_de_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/halt_hold1_ex_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R15C24[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/rst_fptr_align_de_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1 | R15C24[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/rst_fptr_align_de_s0/Q |
2.415 | 0.236 | tNET | RR | 1 | R15C24[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/halt_hold1_ex_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R15C24[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/halt_hold1_ex_s0/CLK |
1.845 | 0.000 | tHld | 1 | R15C24[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_cortexm1/u_core/u_ctrl/u_excpt/halt_hold1_ex_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.236, 41.492%; tC2Q: 0.333, 58.508% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -2.482 |
Data Arrival Time | 135.120 |
Data Required Time | 132.638 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/TDOi_s1 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[F] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
129.630 | 129.630 | active clock edge time | ||||
129.630 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
131.290 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
131.534 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
131.992 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
135.120 | 3.128 | tNET | FF | 1 | IOR15[B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/TDOi_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
130.000 | 130.000 | active clock edge time | ||||
130.000 | 0.000 | TCLK_JTAG_Soft | ||||
130.000 | 0.000 | tCL | FF | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
130.984 | 0.984 | tINS | FF | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
132.711 | 1.727 | tNET | FF | 1 | IOR15[B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/TDOi_s1/CLK |
132.681 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/TDOi_s1 | |||
132.638 | -0.043 | tSu | 1 | IOR15[B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/TDOi_s1 |
Path Statistics:
Clock Skew | 0.807 |
Setup Relationship | 0.370 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.984, 36.306%; route: 1.727, 63.694% |
Path2
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R7C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R7C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync_reg_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync_reg_s0 | |||
262.270 | -0.043 | tSu | 1 | R7C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync_reg_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path3
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync2_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R7C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync2_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R7C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync2_reg_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync2_reg_s0 | |||
262.270 | -0.043 | tSu | 1 | R7C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCSYSPWRUPACK/sync2_reg_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path4
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R5C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R5C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync_reg_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync_reg_s0 | |||
262.270 | -0.043 | tSu | 1 | R5C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync_reg_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path5
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync2_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R5C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync2_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R5C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync2_reg_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync2_reg_s0 | |||
262.270 | -0.043 | tSu | 1 | R5C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uCDBGPWRUPACK/sync2_reg_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path6
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R4C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R4C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync_reg_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync_reg_s0 | |||
262.270 | -0.043 | tSu | 1 | R4C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync_reg_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path7
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync2_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R4C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync2_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R4C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync2_reg_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync2_reg_s0 | |||
262.270 | -0.043 | tSu | 1 | R4C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPSwDpSync/uSyncBusAck/sync2_reg_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path8
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R5C2[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R5C2[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0 | |||
262.270 | -0.043 | tSu | 1 | R5C2[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busreq_cdc_check_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path9
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CSYSPWRUPREQ_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R7C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CSYSPWRUPREQ_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R7C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CSYSPWRUPREQ_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CSYSPWRUPREQ_s0 | |||
262.270 | -0.043 | tSu | 1 | R7C4[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CSYSPWRUPREQ_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path10
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CDBGPWRUPREQ_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R5C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CDBGPWRUPREQ_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R5C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CDBGPWRUPREQ_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CDBGPWRUPREQ_s0 | |||
262.270 | -0.043 | tSu | 1 | R5C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/CDBGPWRUPREQ_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path11
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busabort_cdc_check_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R5C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busabort_cdc_check_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R5C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busabort_cdc_check_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busabort_cdc_check_s0 | |||
262.270 | -0.043 | tSu | 1 | R5C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpIMux/Busabort_cdc_check_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path12
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Optr_s2 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R2C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Optr_s2/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R2C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Optr_s2/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Optr_s2 | |||
262.270 | -0.043 | tSu | 1 | R2C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Optr_s2 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path13
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Busreqi_s1 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R4C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Busreqi_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R4C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Busreqi_s1/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Busreqi_s1 | |||
262.270 | -0.043 | tSu | 1 | R4C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Busreqi_s1 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path14
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APdir_cdc_check_s1 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R5C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APdir_cdc_check_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R5C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APdir_cdc_check_s1/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APdir_cdc_check_s1 | |||
262.270 | -0.043 | tSu | 1 | R5C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/APdir_cdc_check_s1 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path15
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Iptr_s1 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R2C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Iptr_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R2C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Iptr_s1/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Iptr_s1 | |||
262.270 | -0.043 | tSu | 1 | R2C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Iptr_s1 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path16
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Transapdp_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R3C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Transapdp_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R3C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Transapdp_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Transapdp_s0 | |||
262.270 | -0.043 | tSu | 1 | R3C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Transapdp_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path17
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickyerr_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R5C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickyerr_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R5C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickyerr_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickyerr_s0 | |||
262.270 | -0.043 | tSu | 1 | R5C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickyerr_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path18
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickycmp_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R7C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickycmp_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R7C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickycmp_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickycmp_s0 | |||
262.270 | -0.043 | tSu | 1 | R7C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Stickycmp_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path19
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_0_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R8C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R8C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_0_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_0_s0 | |||
262.270 | -0.043 | tSu | 1 | R8C4[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_0_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path20
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_1_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R7C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R7C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_1_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_1_s0 | |||
262.270 | -0.043 | tSu | 1 | R7C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/DPaddr_1_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path21
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_0_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R9C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R9C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_0_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_0_s0 | |||
262.270 | -0.043 | tSu | 1 | R9C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_0_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path22
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_1_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R6C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R6C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_1_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_1_s0 | |||
262.270 | -0.043 | tSu | 1 | R6C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_1_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path23
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_2_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R9C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R9C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_2_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_2_s0 | |||
262.270 | -0.043 | tSu | 1 | R9C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_2_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path24
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_3_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R9C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R9C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_3_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_3_s0 | |||
262.270 | -0.043 | tSu | 1 | R9C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_3_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Path25
Path Summary:
Slack | -2.480 |
Data Arrival Time | 264.750 |
Data Required Time | 262.270 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_4_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | TCLK_JTAG_Soft:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
259.259 | 259.259 | active clock edge time | ||||
259.259 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
260.920 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
261.164 | 0.244 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
261.622 | 0.458 | tC2Q | RF | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
264.750 | 3.128 | tNET | FF | 1 | R7C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
260.000 | 260.000 | active clock edge time | ||||
260.000 | 0.000 | TCLK_JTAG_Soft | ||||
260.000 | 0.000 | tCL | RR | 1 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/I |
260.982 | 0.982 | tINS | RR | 324 | IOB15[A] | Gowin_EMPU_M1_Top_1/JTAG_9_ibuf/O |
262.343 | 1.361 | tNET | RR | 1 | R7C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_4_s0/CLK |
262.313 | -0.030 | tUnc | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_4_s0 | |||
262.270 | -0.043 | tSu | 1 | R7C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPJtagDpProtocol/Buswdatai_cdc_check_4_s0 |
Path Statistics:
Clock Skew | 0.439 |
Setup Relationship | 0.741 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.244, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 3.128, 87.220%; tC2Q: 0.458, 12.780% |
Required Clock Path Delay | cell: 0.982, 41.904%; route: 1.361, 58.096% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R2C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R2C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync_reg_s0/CLK |
1.860 | 0.015 | tHld | 1 | R2C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path2
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync2_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R2C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync2_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R2C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync2_reg_s0/CLK |
1.860 | 0.015 | tHld | 1 | R2C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusAbort/sync2_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path3
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R5C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R5C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0/CLK |
1.860 | 0.015 | tHld | 1 | R5C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path4
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync2_reg_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R5C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync2_reg_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R5C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync2_reg_s0/CLK |
1.860 | 0.015 | tHld | 1 | R5C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbSync/uSyncBusReq/sync2_reg_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path5
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscmpi_cdc_check_s1 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R11C2[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscmpi_cdc_check_s1/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R11C2[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscmpi_cdc_check_s1/CLK |
1.860 | 0.015 | tHld | 1 | R11C2[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscmpi_cdc_check_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path6
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_0_s3 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C6[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C6[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_0_s3/CLK |
1.860 | 0.015 | tHld | 1 | R8C6[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_0_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path7
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_1_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C6[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C6[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_1_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C6[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/APBcurr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path8
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buserrori_cdc_check_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buserrori_cdc_check_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buserrori_cdc_check_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C5[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buserrori_cdc_check_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path9
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Busacki_cdc_check_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R9C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Busacki_cdc_check_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Busacki_cdc_check_s0/CLK |
1.860 | 0.015 | tHld | 1 | R9C4[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Busacki_cdc_check_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path10
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_0_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_0_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path11
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_1_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R9C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_1_s0/CLK |
1.860 | 0.015 | tHld | 1 | R9C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path12
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_2_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_2_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C2[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path13
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_3_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R9C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_3_s0/CLK |
1.860 | 0.015 | tHld | 1 | R9C2[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path14
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path15
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path16
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C3[2][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path17
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C2[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path18
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C2[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path19
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C2[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path20
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C3[1][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path21
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R8C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R8C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0/CLK |
1.860 | 0.015 | tHld | 1 | R8C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Buscnt_cdc_check_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path22
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_0_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R9C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R9C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_0_s0/CLK |
1.860 | 0.015 | tHld | 1 | R9C3[0][B] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path23
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_1_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R11C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R11C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_1_s0/CLK |
1.860 | 0.015 | tHld | 1 | R11C3[0][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path24
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_2_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R13C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R13C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_2_s0/CLK |
1.860 | 0.015 | tHld | 1 | R13C3[2][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Path25
Path Summary:
Slack | 2.095 |
Data Arrival Time | 3.955 |
Data Required Time | 1.860 |
From | Gowin_EMPU_M1_Top_1/dbgRstGen_s0 |
To | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_3_s0 |
Launch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Latch Clk | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/CLK |
2.178 | 0.333 | tC2Q | RR | 1006 | IOL5[A] | Gowin_EMPU_M1_Top_1/dbgRstGen_s0/Q |
3.955 | 1.776 | tNET | RR | 1 | R11C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | Gowin_rPLL_1/rpll_inst/CLKOUT.default_gen_clk | ||||
1.661 | 1.661 | tCL | RR | 2358 | PLL_R | Gowin_rPLL_1/rpll_inst/CLKOUT |
1.845 | 0.185 | tNET | RR | 1 | R11C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_3_s0/CLK |
1.860 | 0.015 | tHld | 1 | R11C3[1][A] | Gowin_EMPU_M1_Top_1/M1_inst/u_CortexM1DbgIntegration_inst/u_swj_dp/uDAPDpApbIf/Rdbuff_cdc_check_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.776, 84.199%; tC2Q: 0.333, 15.801% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.185, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 7.621 |
Actual Width: | 8.871 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_1kHz_4 |
Objects: | REG_LCD_STR1_POZ0_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_1kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_1kHz_s1/Q |
12.379 | 2.379 | tNET | FF | REG_LCD_STR1_POZ0_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_1kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_1kHz_s1/Q |
21.250 | 1.250 | tNET | RR | REG_LCD_STR1_POZ0_6_s0/CLK |
MPW2
MPW Summary:
Slack: | 7.621 |
Actual Width: | 8.871 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_1kHz_4 |
Objects: | REG_LCD_STR1_POZ11_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_1kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_1kHz_s1/Q |
12.379 | 2.379 | tNET | FF | REG_LCD_STR1_POZ11_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_1kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_1kHz_s1/Q |
21.250 | 1.250 | tNET | RR | REG_LCD_STR1_POZ11_2_s0/CLK |
MPW3
MPW Summary:
Slack: | 7.621 |
Actual Width: | 8.871 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_1kHz_4 |
Objects: | REG_LCD_STR1_POZ0_5_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_1kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_1kHz_s1/Q |
12.379 | 2.379 | tNET | FF | REG_LCD_STR1_POZ0_5_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_1kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_1kHz_s1/Q |
21.250 | 1.250 | tNET | RR | REG_LCD_STR1_POZ0_5_s1/CLK |
MPW4
MPW Summary:
Slack: | 7.708 |
Actual Width: | 8.958 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_2kHz_4 |
Objects: | en_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_2kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_2kHz_s1/Q |
12.362 | 2.362 | tNET | FF | en_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_2kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_2kHz_s1/Q |
21.320 | 1.320 | tNET | RR | en_s0/CLK |
MPW5
MPW Summary:
Slack: | 7.708 |
Actual Width: | 8.958 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_2kHz_4 |
Objects: | counter_s_9_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_2kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_2kHz_s1/Q |
12.362 | 2.362 | tNET | FF | counter_s_9_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_2kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_2kHz_s1/Q |
21.320 | 1.320 | tNET | RR | counter_s_9_s1/CLK |
MPW6
MPW Summary:
Slack: | 7.708 |
Actual Width: | 8.958 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_2kHz_4 |
Objects: | counter_s_5_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_2kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_2kHz_s1/Q |
12.362 | 2.362 | tNET | FF | counter_s_5_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_2kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_2kHz_s1/Q |
21.320 | 1.320 | tNET | RR | counter_s_5_s1/CLK |
MPW7
MPW Summary:
Slack: | 7.708 |
Actual Width: | 8.958 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_2kHz_4 |
Objects: | counter_s_3_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_2kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_2kHz_s1/Q |
12.362 | 2.362 | tNET | FF | counter_s_3_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_2kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_2kHz_s1/Q |
21.320 | 1.320 | tNET | RR | counter_s_3_s1/CLK |
MPW8
MPW Summary:
Slack: | 7.708 |
Actual Width: | 8.958 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_2kHz_4 |
Objects: | counter_s_2_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_2kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_2kHz_s1/Q |
12.362 | 2.362 | tNET | FF | counter_s_2_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_2kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_2kHz_s1/Q |
21.320 | 1.320 | tNET | RR | counter_s_2_s1/CLK |
MPW9
MPW Summary:
Slack: | 7.708 |
Actual Width: | 8.958 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_2kHz_4 |
Objects: | counter_s_4_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_2kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_2kHz_s1/Q |
12.362 | 2.362 | tNET | FF | counter_s_4_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_2kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_2kHz_s1/Q |
21.320 | 1.320 | tNET | RR | counter_s_4_s1/CLK |
MPW10
MPW Summary:
Slack: | 7.708 |
Actual Width: | 8.958 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk_2kHz_4 |
Objects: | counter_s_8_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | clk_2kHz_4 | ||
10.000 | 0.000 | tCL | FF | clk_2kHz_s1/Q |
12.362 | 2.362 | tNET | FF | counter_s_8_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
20.000 | 0.000 | active clock edge time | ||
20.000 | 0.000 | clk_2kHz_4 | ||
20.000 | 0.000 | tCL | RR | clk_2kHz_s1/Q |
21.320 | 1.320 | tNET | RR | counter_s_8_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
2358 | clkout_o_PLL | -10.906 | 0.262 |
1444 | n929_6 | 14.174 | 2.462 |
1006 | dbgRstGen | 12.949 | 3.613 |
324 | JTAG_9_1 | -26.482 | 1.727 |
180 | biu_rdy | -2.777 | 3.122 |
169 | IOADDR_Z[4] | 0.729 | 5.089 |
147 | IOADDR_Z[3] | 1.140 | 3.794 |
147 | dap_ext_dsel | 3.993 | 4.450 |
100 | iDBGDI_3 | -26.482 | 3.000 |
96 | hold_reg2_mask | 6.158 | 4.101 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R7C7 | 97.22% |
R6C8 | 95.83% |
R11C22 | 94.44% |
R18C19 | 94.44% |
R8C7 | 94.44% |
R16C19 | 94.44% |
R6C5 | 93.06% |
R6C7 | 93.06% |
R11C5 | 93.06% |
R16C26 | 93.06% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|